1. Field of the Invention
This invention relates to the time dependent electrical breakdown of dielectric layers, and in particular to those layers used as insulators in the semiconductor industry where accelerated testing is desirable to reduce qualification time.
2. Description of Related Art
Advances in the art of semiconductor processing have dramatically increased the number of functional elements on a semiconductor chip. This has been accomplished by increasing the size of the chip somewhat, but more importantly, by reducing the size of the minimum feature (the design rule) on the chip. A one micron design rule was common for a 1 MB DRAM design, and a 0.18 micron design rule is being considered for a 1 GB DRAM. The dielectric layers separating these features is also being scaled down in thickness, making the qualification of these layers and the prediction of their lifetime reliability ever more important.
Improvements in processing have also made dielectric layers lifetimes increase, which increases the time and sample size needed to qualify a new process. Further, increased competition in the semiconductor industry has reduced design cycle times to a few months. Accelerated stress testing is used to reduce the time to observe failures, and temperature is one factor which is used in accelerated testing to get a specific fraction of the test population to fail.
Many chemical and physical processes leading to failure are accelerated by temperature in a way that can be readily modeled and reproduced. The relation between reaction rates and temperature is expressed by the well known Arrhenius relationship EQU R=R.sub.o exp[-E.sub.a /kT]
where
R=Reaction Rate PA2 Ro=a constant PA2 Ea=activation energy, in electron volts PA2 K=Boltzman's constant, 8.6(10)-5 eV/deg.K PA2 T=absolute temperature, deg. K.
This can be conveniently expressed in graphical form by plotting reciprocal temperature versus log time for a constant fraction of failure. If the Arrhenious relationship holds, the plot is linear and the slope is related to k/E.sub.a.
Reducing testing time therefore requires higher test temperature, which in turn places a burden on test fixtures and which can cause spurious effects within the device under test. For example, present testing is done at a temperature of 174 degrees Centigrade for four weeks using test probes which are gold plated, mounted in acrylic and utilize point to point wiring. These materials fail at temperatures like 300 degrees Centigrade which would significantly reduce test times. The gold interdiffuses with aluminum test pads to form a brittle intermetallic compound, and polymer substrates simply melt, prior to charring. Attempts have been made to water cool the test fixture, but this is awkward and often not available in so called "dry" electrical laboratories.
Testing with metal-oxide-silicon devices produces polarity effects where the applied voltage is not completely distributed across the dielectric due to space charge effects so the tests are polarity dependent.
Accordingly, there is a need in the art for a test structure and its associated fixtures which can apply a known electrical field across a dielectric layer at temperatures around 300 degrees Centigrade.